Giant mixed process battles, the smaller the chip is really the better?

Recently, there has been a lot of news about the giants catching up with each other in advanced chip processes.

First, the old chipmaker IBM announced the development of 2nm chips, followed by TSMC announced a major achievement: the discovery of two-dimensional materials combined with semi-metallic bismuth (Bi) can achieve very low resistance, close to the quantum limit, can meet the needs of the 1nm process.

Giant mixed process battles, the smaller the chip is really the better?

IBM’s 2nm wafers

Why are the chip giants pursuing smaller process chips? Is a smaller chip really better? In addition to improving the performance of cell phones, what are the other applications of smaller chips for us ordinary people?

According to Zhao Zhanxiang, partner and CTO of Yunxui Capital, there are many reasons for the giants to pursue smaller process: “First, it can significantly increase the density of transistors; second, it will bring a significant increase in performance – in the case of CPUs, for example, a process evolution is a 50% improvement in performance. Intel’s backwardness in process has limited his performance improvement for some time; third, it can bring lower power consumption, which is in higher demand in mobile devices and data centers, and for data centers, the power consumption optimization per TOPS/W can bring nearly a hundred dollars of power consumption, operation and maintenance cost reduction. “

Also, demand-driven. “Currently, the main driver is in the cell phone CPU, tablet CPU, personal computer or server CPU, GPU chips, various AI chips, and FPGA chips, including a part of the virtual currency miner chips, etc., mainly in pursuit of higher data processing power, or higher integration of the chip on the application scenario. ” Lu Xiaobao, managing director of CSTC, believes.

But the chip process does not go on infinitely small.

AMD senior digital chip design engineer Wen Ge said that the current 3nm is basically close to the process limit. “After the process reaches below 7nm, the short-channel effect and quantum attempt to penetrate the effect will become more and more obvious, which will bring great challenges to the process. In addition, the diameter of silicon atoms is around 0.117nm, and the channel length of 1nm is less than the width of 9 atoms, which is very difficult to achieve from the physical level.”

In addition, “as the gate size shrinks, the gate’s ability to control the current decreases and leakage increases thus can lead to chip failure.” Qiao Tong, PhD in physics at Nanjing University, added.

And smaller process chips, “the future of AI and autonomous driving and other scenarios may benefit. But on the cell phone side, it can be said that no new application scenarios have emerged, and even the current processor performance for cell phones, is already excessive.” Wen Ge believes that.

In this issue of “You Ask, I Answer”, we invite industry insiders to discuss with you. The following are excerpts from the highlights.

The pursuit of smaller process can improve performance and reduce power consumption
@Zhanxiang Zhao, Partner and CTO of Yunxui Capital

The width of the gate determines the loss of current through the gate, which is the common heat and power consumption of cell phones. However, with the development of advanced process, 5nm and 3nm no longer represent the minimum line width of the gate, but the equivalent length.

Giant mixed process battles, the smaller the chip is really the better?

Image from the network

There are many reasons for the giant to pursue a smaller process: first, it can significantly increase the density of transistors; second, it will bring a significant increase in performance – in the case of CPU, for example, the evolution of a process is a 50% performance improvement, Intel’s backwardness in the process has limited his performance improvement for some time; third, it can bring lower power consumption, which is in higher demand in mobile devices and data centers, and for data centers, the optimization of power consumption per TOPS/W can bring nearly a hundred dollars in electricity consumption, operation and maintenance cost reduction.

Giant mixed process battles, the smaller the chip is really the better?

Image from the network

But on the other hand, as the process continues to approach the physical limits, the cost of the chip itself, once the process advances brought about significant cost optimization is no longer significant, it is now mainly the demand for materials and structures, equipment and so on that has led to soaring manufacturing costs.

@Lu Xiaobao, Managing Director of CSTC

At present, it is mainly some international giants, such as TSMC, Intel, Samsung, etc., who are continuing to promote advanced semiconductor processes.

The iteration of semiconductor manufacturing processes is mainly driven by Moore’s theorem, which states that the number of transistors that can be accommodated on an integrated circuit doubles approximately every 18 months. The existence of Moore’s theorem means that the price of a chip product with the same performance decreases by 50% every 18 months, or that the performance of an IC product with the same price increases by 100% every 18 months.

Moore’s theorem is an industrial development plan led by industry giants, driving and prompting all enterprises in all segments of the upstream and downstream chains of the entire industry to develop synergies at the same pace, with each segment neither too fast nor too slow. To some extent, Moore’s theorem coordinates the development rhythm of the entire IC industry, which can be said to be the semiconductor industry’s “fifty-year plan”.

However, after more than 50 years of development, Moore’s theorem has been declining, although the advanced process is still progressing almost continuously along the planning of Moore’s theorem, but its technical complexity is becoming more and more difficult and costly to achieve, and fewer and fewer chip products can afford the high R&D and manufacturing costs.

At present, mainly cell phone CPUs, tablet CPUs, personal computer CPUs, GPUs, etc., which are very sensitive to performance improvement, or scenarios where the demand for computing power continues to rise such as various AI chips and mining chips, etc. Inside these scenarios, the chip performance improvement brought by advanced processes is still sufficient to offset the significant increase in chip R&D costs.

But more and more application scenarios, more and more types of chips, after reaching the threshold point of performance, it is no longer meaningful to continue to improve the integration degree. The use of advanced processes, one-time R & D and production investment burden is too heavy, instead of using mature processes such as 28nm, 40nm, 55nm, or even 8-inch process, the cost performance will be higher, such as TWS headset chip, watch chip, a variety of car chip, a variety of home appliances chip, IoT chip, etc..

In addition, due to the rapid increase in advanced process development and manufacturing costs, the cost of improving chip performance/integration through chip manufacturing is rising too fast, and the input-output ratio is getting smaller and smaller, but the demand side still has the requirement to continuously improve performance/integration.

In this contradiction, also forced the industry to find another way, began to think through other technical ways, such as packaging technology to enhance the chip performance / integration, chiplet technology also began to rapidly promote the application. Through chiplet technology, the use of 10nm process manufacturing out of the chip, fully can also reach 7nm chip integration, but the investment in research and development and one-time production investment is much less than the investment in 7nm chip.

3nm chips, already close to process limits
@wingo AMD Senior Digital Chip Design Engineer

To say that the chip process naming, that is certainly TSMC play the most slippery.

Giant mixed process battles, the smaller the chip is really the better?

The above chart is a comparison of the transistor gate widths of Intel 14nm and TSMC 10nm, which in fact are not too far apart.

The nm in the 5nm and 3nm process refers to the length of the transistor’s conductive channel, which is also usually considered to be the transistor’s gate width.

The gate of a transistor is the narrowest line in the entire chip circuit. If the gate width is 3nm, it is referred to as a 3nm process.

The current 3nm process has basically connected into the process limit. In the era of FinFET transistors, i.e., below 22nm, the process grade is no longer the true channel length, but the equivalent process grade calculated based on transistor density and chip area.

In terms of silicon-based chips, the process is no way to stay small, after the process reaches 7nm or less, the short channel effect and the quantum attempt to penetrate the effect will become more and more obvious, which will bring great challenges to the process. In addition, the diameter of silicon atoms is around 0.117nm, and the channel length of 1nm is less than the width of 9 atoms, which is very difficult to achieve from the physical level.

At 5nm and below, the input-output ratio of chips with smaller processes is getting lower and lower, which is very unreasonable. If it’s not oligopoly, then TSMC must be losing money.

@ Qiaotong PhD in Physics, Nanjing University

With the progress of semiconductor process technology, the size of the chip is getting smaller and smaller, and has entered the era of sub-10nm.

Originally, the nanometer number of the chip refers to the length of the transistor gate, representing the level of the chip manufacturing process, but the current state-of-the-art 5nm and 3nm are just process codes, and are no longer the physical length of the gate.

Because as the size of the gate shrinks, the gate’s ability to control the current decreases, leakage increases thus leading to chip failure. In addition, the size of the reduction to a certain extent will appear quantum effect, which is also the reason for the restriction of the chip to shrink without limit.

But the use of more advanced process chip performance is stronger, lower power consumption, so technology giants such as Huawei, Apple, etc. are tirelessly pursuing smaller chip size.

There are two major problems with the shrinking of the chip: one is the increasing complexity of the manufacturing process, the second is the increasing cost. The shrinking size of the chip has led to a significant increase in process steps, and the cost continues to rise, so fewer companies can afford it.

With the booming development of 5G, AI, smart electric vehicles and other industries, the industry’s demand for advanced process chips continues to rise, and it is expected that more and more companies will balance chip size and chip cost in the future and choose the right process for them.

Future application scenarios: AI, mining, autonomous driving
@Siao-Bao Lu Managing Director of CSCT

Advanced processes such as 7nm and 5nm process are currently mainly applied in cell phone CPU, tablet CPU, PC or server CPU, GPU chips, various AI chips, and FPGA chips, including a part of virtual currency mining chips, etc. The main application scenario is to pursue higher data processing capability, or higher integration of chips.

Among the typical consumer applications are mainly cell phones, tablet PCs, PCs, etc..

Other consumer applications such as TWS headphones, watches, bracelets and other digital products CPU chips, basically 28nm, 22nm as the mainstream process platform for production, related products applied to other chips such as communications, storage, sensors, power, etc., are 28nm, 40nm, 65nm and a variety of mature processes, even sensors, power applications are 8-inch process.

@wingo AMD senior digital chip design engineer

With the current situation, the process improvement will bring higher performance, and scenarios such as AI and autonomous driving may benefit in the future. On the cell phone side, it can be said and new application scenarios emerge, even the current processor performance is already too much for cell phones.

Posted by:CoinYuppie,Reprinted with attribution to:https://coinyuppie.com/giant-mixed-process-battles-the-smaller-the-chip-is-really-the-better/
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